/******************************************************************************* MPLAB Harmony System Configuration Header File Name: system_config.h Summary: Build-time configuration header for the system defined by this MPLAB Harmony project. Description: An MPLAB Project may have multiple configurations. This file defines the build-time options for a single configuration. Remarks: This configuration header must not define any prototypes or data definitions (or include any files that do). It only provides macro definitions for build-time configuration options that are not instantiated until used by another MPLAB Harmony module or application. Created with MPLAB Harmony Version 2.05 *******************************************************************************/ // DOM-IGNORE-BEGIN /******************************************************************************* Copyright (c) 2013-2015 released Microchip Technology Inc. All rights reserved. Microchip licenses to you the right to use, modify, copy and distribute Software only when embedded on a Microchip microcontroller or digital signal controller that is integrated into your product or third party product (pursuant to the sublicense terms in the accompanying license agreement). You should refer to the license agreement accompanying this Software for additional information regarding your rights and obligations. SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. *******************************************************************************/ // DOM-IGNORE-END #ifndef _SYSTEM_CONFIG_H #define _SYSTEM_CONFIG_H // ***************************************************************************** // ***************************************************************************** // Section: Included Files // ***************************************************************************** // ***************************************************************************** /* This section Includes other configuration headers necessary to completely define this configuration. */ #include "bsp.h" // DOM-IGNORE-BEGIN #ifdef __cplusplus // Provide C++ Compatibility extern "C" { #endif // DOM-IGNORE-END // ***************************************************************************** // ***************************************************************************** // Section: System Service Configuration // ***************************************************************************** // ***************************************************************************** // ***************************************************************************** /* Common System Service Configuration Options */ #define SYS_VERSION_STR "2.05" #define SYS_VERSION 20500 // ***************************************************************************** /* Clock System Service Configuration Options */ #define SYS_CLK_FREQ 200000000ul #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul #define SYS_CLK_CONFIG_PRIMARY_XTAL 24000000ul #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul /*** Ports System Service Configuration ***/ #define SYS_PORT_A_ANSEL 0xFFC2 #define SYS_PORT_A_TRIS 0xFFDE #define SYS_PORT_A_LAT 0x0000 #define SYS_PORT_A_ODC 0x0000 #define SYS_PORT_A_CNPU 0x001C #define SYS_PORT_A_CNPD 0x0000 #define SYS_PORT_A_CNEN 0x0000 #define SYS_PORT_B_ANSEL 0x3FDC #define SYS_PORT_B_TRIS 0x3FDC #define SYS_PORT_B_LAT 0x0000 #define SYS_PORT_B_ODC 0x0000 #define SYS_PORT_B_CNPU 0x0000 #define SYS_PORT_B_CNPD 0x0000 #define SYS_PORT_B_CNEN 0x0000 #define SYS_PORT_D_ANSEL 0x7BFF #define SYS_PORT_D_TRIS 0xFFFF #define SYS_PORT_D_LAT 0x0000 #define SYS_PORT_D_ODC 0x0000 #define SYS_PORT_D_CNPU 0x0000 #define SYS_PORT_D_CNPD 0x0000 #define SYS_PORT_D_CNEN 0x0000 #define SYS_PORT_E_ANSEL 0xFFA7 #define SYS_PORT_E_TRIS 0xFFA7 #define SYS_PORT_E_LAT 0x0000 #define SYS_PORT_E_ODC 0x0000 #define SYS_PORT_E_CNPU 0x0000 #define SYS_PORT_E_CNPD 0x0000 #define SYS_PORT_E_CNEN 0x0000 #define SYS_PORT_F_ANSEL 0xFFEF #define SYS_PORT_F_TRIS 0xFFFF #define SYS_PORT_F_LAT 0x0000 #define SYS_PORT_F_ODC 0x0000 #define SYS_PORT_F_CNPU 0x0000 #define SYS_PORT_F_CNPD 0x0000 #define SYS_PORT_F_CNEN 0x0000 #define SYS_PORT_G_ANSEL 0xCFFF #define SYS_PORT_G_TRIS 0xDFFF #define SYS_PORT_G_LAT 0x0000 #define SYS_PORT_G_ODC 0x0000 #define SYS_PORT_G_CNPU 0x1000 #define SYS_PORT_G_CNPD 0x0000 #define SYS_PORT_G_CNEN 0x0000 /*** Interrupt System Service Configuration ***/ #define SYS_INT true /*** Timer System Service Configuration ***/ #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 #define SYS_TMR_FREQUENCY 1000 #define SYS_TMR_FREQUENCY_TOLERANCE 10 #define SYS_TMR_UNIT_RESOLUTION 10000 #define SYS_TMR_CLIENT_TOLERANCE 10 #define SYS_TMR_INTERRUPT_NOTIFICATION true // ***************************************************************************** // ***************************************************************************** // Section: Driver Configuration // ***************************************************************************** // ***************************************************************************** /*** Timer Driver Configuration ***/ #define DRV_TMR_INTERRUPT_MODE true #define DRV_TMR_INSTANCES_NUMBER 1 #define DRV_TMR_CLIENTS_NUMBER 1 /*** Timer Driver 0 Configuration ***/ #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_1 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_1 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T1 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_1_VECTOR #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL1 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_256 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false #define DRV_TMR_POWER_STATE_IDX0 SYS_MODULE_POWER_RUN_FULL // ***************************************************************************** /* USART Driver Configuration Options */ #define DRV_USART_INTERRUPT_MODE false #define DRV_USART_BYTE_MODEL_SUPPORT false #define DRV_USART_READ_WRITE_MODEL_SUPPORT true #define DRV_USART_BUFFER_QUEUE_SUPPORT true #define DRV_USART_CLIENTS_NUMBER 1 #define DRV_USART_INSTANCES_NUMBER 1 #define DRV_USART_PERIPHERAL_ID_IDX0 USART_ID_1 #define DRV_USART_OPER_MODE_IDX0 DRV_USART_OPERATION_MODE_NORMAL #define DRV_USART_OPER_MODE_DATA_IDX0 #define DRV_USART_INIT_FLAG_WAKE_ON_START_IDX0 false #define DRV_USART_INIT_FLAG_AUTO_BAUD_IDX0 false #define DRV_USART_INIT_FLAG_STOP_IN_IDLE_IDX0 false #define DRV_USART_INIT_FLAGS_IDX0 0 #define DRV_USART_BRG_CLOCK_IDX0 100000000 #define DRV_USART_BAUD_RATE_IDX0 115200 #define DRV_USART_LINE_CNTRL_IDX0 DRV_USART_LINE_CONTROL_8NONE1 #define DRV_USART_HANDSHAKE_MODE_IDX0 DRV_USART_HANDSHAKE_NONE #define DRV_USART_LINES_ENABLE_IDX0 USART_ENABLE_TX_RX_USED #define DRV_USART_XMIT_INT_SRC_IDX0 INT_SOURCE_USART_1_TRANSMIT #define DRV_USART_RCV_INT_SRC_IDX0 INT_SOURCE_USART_1_RECEIVE #define DRV_USART_ERR_INT_SRC_IDX0 INT_SOURCE_USART_1_ERROR #define DRV_USART_XMIT_QUEUE_SIZE_IDX0 10 #define DRV_USART_RCV_QUEUE_SIZE_IDX0 10 #define DRV_USART_POWER_STATE_IDX0 SYS_MODULE_POWER_RUN_FULL #define DRV_USART_QUEUE_DEPTH_COMBINED 20 // ***************************************************************************** // ***************************************************************************** // Section: Middleware & Other Library Configuration // ***************************************************************************** // ***************************************************************************** // ***************************************************************************** // Section: Bootloader NVM Driver Configuration // ***************************************************************************** /* NVM Driver Flash Memory row and page size in bytes */ #define USE_PAGE_ERASE 0 #define USE_QUAD_WORD_WRITE 1 // ***************************************************************************** /* BSP Configuration Options */ #define BSP_OSC_FREQUENCY 24000000 // ***************************************************************************** // ***************************************************************************** // Section: Application Configuration // ***************************************************************************** // ***************************************************************************** /*** Application Defined Pins ***/ /*** Functions for BSP_LED_3 pin ***/ #define BSP_LED_3Toggle() PLIB_PORTS_PinToggle(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_6) #define BSP_LED_3On() PLIB_PORTS_PinSet(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_6) #define BSP_LED_3Off() PLIB_PORTS_PinClear(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_6) #define BSP_LED_3StateGet() PLIB_PORTS_PinGetLatched(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_6) /*** Functions for BSP_RGB_LED_RED pin ***/ #define BSP_RGB_LED_REDToggle() PLIB_PORTS_PinToggle(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_5) #define BSP_RGB_LED_REDOn() PLIB_PORTS_PinClear(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_5) #define BSP_RGB_LED_REDOff() PLIB_PORTS_PinSet(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_5) #define BSP_RGB_LED_REDStateGet() (!(PLIB_PORTS_PinGetLatched(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_5))) /*** Functions for BSP_RGB_LED_GREEN pin ***/ #define BSP_RGB_LED_GREENToggle() PLIB_PORTS_PinToggle(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_1) #define BSP_RGB_LED_GREENOn() PLIB_PORTS_PinClear(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_1) #define BSP_RGB_LED_GREENOff() PLIB_PORTS_PinSet(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_1) #define BSP_RGB_LED_GREENStateGet() (!(PLIB_PORTS_PinGetLatched(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_1))) /*** Functions for BSP_RGB_LED_BLUE pin ***/ #define BSP_RGB_LED_BLUEToggle() PLIB_PORTS_PinToggle(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_0) #define BSP_RGB_LED_BLUEOn() PLIB_PORTS_PinClear(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_0) #define BSP_RGB_LED_BLUEOff() PLIB_PORTS_PinSet(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_0) #define BSP_RGB_LED_BLUEStateGet() (!(PLIB_PORTS_PinGetLatched(PORTS_ID_0, PORT_CHANNEL_B, PORTS_BIT_POS_0))) /*** Functions for BSP_LED_1 pin ***/ #define BSP_LED_1Toggle() PLIB_PORTS_PinToggle(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_3) #define BSP_LED_1On() PLIB_PORTS_PinSet(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_3) #define BSP_LED_1Off() PLIB_PORTS_PinClear(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_3) #define BSP_LED_1StateGet() PLIB_PORTS_PinGetLatched(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_3) /*** Functions for BSP_LED_2 pin ***/ #define BSP_LED_2Toggle() PLIB_PORTS_PinToggle(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_4) #define BSP_LED_2On() PLIB_PORTS_PinSet(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_4) #define BSP_LED_2Off() PLIB_PORTS_PinClear(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_4) #define BSP_LED_2StateGet() PLIB_PORTS_PinGetLatched(PORTS_ID_0, PORT_CHANNEL_E, PORTS_BIT_POS_4) /*** Functions for BSP_SWITCH_1 pin ***/ #define BSP_SWITCH_1StateGet() PLIB_PORTS_PinGet(PORTS_ID_0, PORT_CHANNEL_G, PORTS_BIT_POS_12) /*** Functions for BSP_STBY_RST pin ***/ #define BSP_STBY_RSTToggle() PLIB_PORTS_PinToggle(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_5) #define BSP_STBY_RSTOn() PLIB_PORTS_PinSet(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_5) #define BSP_STBY_RSTOff() PLIB_PORTS_PinClear(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_5) #define BSP_STBY_RSTStateGet() PLIB_PORTS_PinGetLatched(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_5) #define BSP_STBY_RSTStateSet(Value) PLIB_PORTS_PinWrite(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_5, Value) /*** Functions for BSP_WIFI_SLEEP pin ***/ #define BSP_WIFI_SLEEPToggle() PLIB_PORTS_PinToggle(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_0) #define BSP_WIFI_SLEEPOn() PLIB_PORTS_PinSet(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_0) #define BSP_WIFI_SLEEPOff() PLIB_PORTS_PinClear(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_0) #define BSP_WIFI_SLEEPStateGet() PLIB_PORTS_PinGetLatched(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_0) #define BSP_WIFI_SLEEPStateSet(Value) PLIB_PORTS_PinWrite(PORTS_ID_0, PORT_CHANNEL_A, PORTS_BIT_POS_0, Value) /*** Functions for BSP_WIFI_INT pin ***/ #define BSP_WIFI_INTStateGet() PLIB_PORTS_PinGet(PORTS_ID_0, PORT_CHANNEL_F, PORTS_BIT_POS_4) /*** Application Instance 0 Configuration ***/ //DOM-IGNORE-BEGIN #ifdef __cplusplus } #endif //DOM-IGNORE-END #endif // _SYSTEM_CONFIG_H /******************************************************************************* End of File */