/* Copyright Statement: * * (C) 2005-2016 MediaTek Inc. All rights reserved. * * This software/firmware and related documentation ("MediaTek Software") are * protected under relevant copyright laws. The information contained herein * is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors. * Without the prior written permission of MediaTek and/or its licensors, * any reproduction, modification, use or disclosure of MediaTek Software, * and information contained herein, in whole or in part, shall be strictly prohibited. * You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software * if you have agreed to and been bound by the applicable license agreement with * MediaTek ("License Agreement") and been granted explicit permission to do so within * the License Agreement ("Permitted User"). If you are not a Permitted User, * please cease any access or use of MediaTek Software immediately. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES * THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES * ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR * SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND * CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE, * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. */ #ifndef __HAL_CACHE_HW_H__ #define __HAL_CACHE_HW_H__ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ #ifndef NULL #ifdef __cplusplus #define NULL (0) /*!< NULL */ #else #define NULL ((void *)(0)) /*!< NULL */ #endif #endif /* structure type to access the CACHE register */ typedef struct { __IO uint32_t CACHE_CON; __IO uint32_t CACHE_OP; __IO uint32_t CACHE_HCNT0L; __IO uint32_t CACHE_HCNT0U; __IO uint32_t CACHE_CCNT0L; __IO uint32_t CACHE_CCNT0U; __IO uint32_t CACHE_HCNT1L; __IO uint32_t CACHE_HCNT1U; __IO uint32_t CACHE_CCNT1L; __IO uint32_t CACHE_CCNT1U; uint32_t RESERVED0[1]; __IO uint32_t CACHE_REGION_EN; uint32_t RESERVED1[16372]; /**< (0x10000-12*4)/4 */ __IO uint32_t CACHE_ENTRY_N[16]; __IO uint32_t CACHE_END_ENTRY_N[16]; } CACHE_REGISTER_T; /* CACHE_CON register definitions */ #define CACHE_CON_MCEN_OFFSET (0) #define CACHE_CON_MCEN_MASK (1<<CACHE_CON_MCEN_OFFSET) #define CACHE_CON_CNTEN0_OFFSET (2) #define CACHE_CON_CNTEN0_MASK (1<<CACHE_CON_CNTEN0_OFFSET) #define CACHE_CON_CNTEN1_OFFSET (3) #define CACHE_CON_CNTEN1_MASK (1<<CACHE_CON_CNTEN1_OFFSET) #define CACHE_CON_CACHESIZE_OFFSET (8) #define CACHE_CON_CACHESIZE_MASK (3<<CACHE_CON_CACHESIZE_OFFSET) /* CACHE_OP register definitions */ #define CACHE_OP_EN_OFFSET (0) #define CACHE_OP_EN_MASK (1<<CACHE_OP_EN_OFFSET) #define CACHE_OP_OP_OFFSET (1) #define CACHE_OP_OP_MASK (15<<CACHE_OP_OP_OFFSET) #define CACHE_OP_TADDR_OFFSET (5) #define CACHE_OP_TADDR_MASK (0x7FFFFFFUL<<CACHE_OP_TADDR_OFFSET) /* CACHE_HCNT0L register definitions */ #define CACHE_HCNT0L_CHIT_CNT0_MASK (0xFFFFFFFFUL<<0) /* CACHE_HCNT0U register definitions */ #define CACHE_HCNT0U_CHIT_CNT0_MASK (0xFFFFUL<<0) /* CACHE_CCNT0L register definitions */ #define CACHE_CCNT0L_CACC_CNT0_MASK (0xFFFFFFFFUL<<0) /* CACHE_CCNT0U register definitions */ #define CACHE_CCNT0U_CACC_CNT0_MASK (0xFFFFUL<<0) /* CACHE_HCNT1L register definitions */ #define CACHE_HCNT1L_CHIT_CNT1_MASK (0xFFFFFFFFUL<<0) /* CACHE_HCNT1U register definitions */ #define CACHE_HCNT1U_CHIT_CNT1_MASK (0xFFFFUL<<0) /* CACHE_CCNT1L register definitions */ #define CACHE_CCNT1L_CACC_CNT1_MASK (0xFFFFFFFFUL<<0) /* CACHE_CCNT1U register definitions */ #define CACHE_CCNT1U_CACC_CNT1_MASK (0xFFFFUL<<0) /* CACHE_ENTRY_N register definitions */ #define CACHE_ENTRY_N_C_MASK (1<<8) #define CACHE_ENTRY_BASEADDR_MASK (0xFFFFFUL<<12) /* CACHE_END_ENTRY_N register definitions */ #define CACHE_END_ENTRY_N_BASEADDR_MASK (0xFFFFFUL<<12) /* memory mapping of MT7687 */ #define CMSYS_L1CACHE_BASE (0x01530000) #define CACHE ((CACHE_REGISTER_T *)CMSYS_L1CACHE_BASE) #endif /* __HAL_CACHE_HW_H__ */