# Viewing and Configuring Clock Frequencies

The F1 - Alveo Shell supports all the clock recipes supported by F1 1.4 Shell as listed in [clock_recipes.csv] (https://github.com/aws/aws-fpga/blob/master/hdk/docs/clock_recipes.csv). In addition, this shell also offers dynamic configuration of clock frequencies through indirect registers residing at PF1-B0 address 0x5C and 0x60.

| PF1-BAR0 Offset | Register Name     | Bit Field | Access | Default | Description                                                                                                                                                                                                                                                                                                                                                                                                          |
| --------------- | ----------------- | --------- | ------ | ------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 0x5C            | CLKWIZ\_IND\_ADDR | 31:0      | RW     | 0x0     | Select which Clock wizard to access:<br>32'h0000\_0000 - 32'0000\_0FFF = clk\_wiz\_a<br>32'h0000\_1000 - 32'0000\_1FFF = clk\_wiz\_b<br>32'h0000\_2000 - 32'0000\_2FFF = clk\_wiz\_c<br><br>Please refer to [PG065](https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf#page=15) for definitions on Clock Wizard Registers and configure clock frequencies from each MMCMs. |
| 0x60            | CLKWIZ\_IND\_DATA | 31:0      | RW     | 0x0     | Writes/Reads to this register initiates indirect write/read access to the Registers of the selected MMCMs addressed by CLKWIZ\_IND\_ADDR.<br><br>NOTE: Read the register twice to capture correct data.<br>                                                                                                                                                                                                          |

Three clock wizard (MMCMs) are instantiated in the F1-Alveo Compatible Shell to clock A/B/C clocks.

Please refer to [PG065](https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf#page=15) for Clocking Wizard Registers, and [Procedure to Change Clock Frequency here](https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf#page=61).