# Amazon FPGA Hardware Development Kit
#
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
#
# Licensed under the Amazon Software License (the "License"). You may not use
# this file except in compliance with the License. A copy of the License is
# located at
#
#    http://aws.amazon.com/asl/
#
# or in the "license" file accompanying this file. This file is distributed on
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
# implied. See the License for the specific language governing permissions and
# limitations under the License.

##################################################################
## Makefile For Vivado compiles and simulations
##################################################################

compile:
	mkdir -p $(SIM_DIR)
	cd $(SIM_DIR) && xsc $(C_FILES) --gcc_compile_options "-I$(C_SDK_USR_INC_DIR)" --gcc_compile_options "-I$(C_SDK_USR_UTILS_DIR)" --gcc_compile_options "-I$(C_COMMON_DIR)/include" --gcc_compile_options "-I$(C_COMMON_DIR)/src" --gcc_compile_options "-I$(C_INC_DIR)"  --gcc_compile_options "-DVIVADO_SIM" --gcc_compile_options "-DSV_TEST" --gcc_compile_options "-DDMA_TEST"
	cd $(SIM_DIR) && xvlog --sv -m64 --define DMA_TEST $(DEFAULT_DEFINES) --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --work xil_defaultlib --relax -f $(SCRIPTS_DIR)/top.vivado.f
	cd $(SIM_DIR) && xelab -m64 --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --timescale 1ps/1ps --debug typical --relax --mt 8 -L axi_clock_converter_v2_1_14 -L generic_baseblocks_v2_1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_15 -L axi_register_slice_v2_1_12 -L fifo_generator_v13_2_1 -L fifo_generator_v13_1_4 -L axi_data_fifo_v2_1_11 -L axi_crossbar_v2_1_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -sv_lib dpi --snapshot tb xil_defaultlib.tb xil_defaultlib.glbl xil_defaultlib.$(TEST)


run:

ifeq ($(TEST),test_null)
	cd $(SIM_DIR) && xsim -R -log $(C_TEST).log $(PLUSARGS) -tclbatch $(SCRIPTS_DIR)/waves.tcl tb
else
	cd $(SIM_DIR) && xsim -R -log $(TEST).log $(PLUSARGS) -tclbatch $(SCRIPTS_DIR)/waves.tcl tb
endif