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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

ila_1 your_instance_name (
	.clk(clk), // input wire clk


	.probe0(WREADY), // input wire [0:0] probe0  
	.probe1( AWADDR), // input wire [63:0]  probe1 
	.probe2( BRESP), // input wire [1:0]  probe2 
	.probe3( BVALID), // input wire [0:0]  probe3 
	.probe4( BREADY), // input wire [0:0]  probe4 
	.probe5( ARADDR), // input wire [63:0]  probe5 
	.probe6( RREADY), // input wire [0:0]  probe6 
	.probe7( WVALID), // input wire [0:0]  probe7 
	.probe8( ARVALID), // input wire [0:0]  probe8 
	.probe9( ARREADY), // input wire [0:0]  probe9 
	.probe10( RDATA), // input wire [511:0]  probe10 
	.probe11( AWVALID), // input wire [0:0]  probe11 
	.probe12( AWREADY), // input wire [0:0]  probe12 
	.probe13( RRESP), // input wire [1:0]  probe13 
	.probe14( WDATA), // input wire [511:0]  probe14 
	.probe15( WSTRB), // input wire [63:0]  probe15 
	.probe16( RVALID), // input wire [0:0]  probe16 
	.probe17( ARPROT), // input wire [2:0]  probe17 
	.probe18( AWPROT), // input wire [2:0]  probe18 
	.probe19( AWID), // input wire [4:0]  probe19 
	.probe20( BID), // input wire [4:0]  probe20 
	.probe21( AWLEN), // input wire [7:0]  probe21 
	.probe22( BUSER), // input wire [0:0]  probe22 
	.probe23( AWSIZE), // input wire [2:0]  probe23 
	.probe24( AWBURST), // input wire [1:0]  probe24 
	.probe25( ARID), // input wire [4:0]  probe25 
	.probe26( AWLOCK), // input wire [0:0]  probe26 
	.probe27( ARLEN), // input wire [7:0]  probe27 
	.probe28( ARSIZE), // input wire [2:0]  probe28 
	.probe29( ARBUSRT), // input wire [1:0]  probe29 
	.probe30( ARLOCK), // input wire [0:0]  probe30 
	.probe31( ARCACHE), // input wire [3:0]  probe31 
	.probe32( AWCACHE), // input wire [3:0]  probe32 
	.probe33( ARREGION), // input wire [3:0]  probe33 
	.probe34( ARQOS), // input wire [3:0]  probe34 
	.probe35( ARUSER), // input wire [0:0]  probe35 
	.probe36( AWREGION), // input wire [3:0]  probe36 
	.probe37( AWQOS), // input wire [3:0]  probe37 
	.probe38( RID), // input wire [4:0]  probe38 
	.probe39( AWUSER), // input wire [0:0]  probe39 
	.probe40( WID), // input wire [0:0]  probe40 
	.probe41( RLAST), // input wire [0:0]  probe41 
	.probe42( RUSER), // input wire [0:0]  probe42  
	.probe43( WLAST) // input wire [0:0]  probe43
);

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file ila_1 when simulating
// the core, ila_1. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.