// ********************************************************************** // * SEGGER Microcontroller GmbH * // * The Embedded Experts * // ********************************************************************** // * * // * (c) 2014 - 2018 SEGGER Microcontroller GmbH * // * (c) 2001 - 2018 Rowley Associates Limited * // * * // * www.segger.com Support: support@segger.com * // * * // ********************************************************************** // * * // * All rights reserved. * // * * // * Redistribution and use in source and binary forms, with or * // * without modification, are permitted provided that the following * // * conditions are met: * // * * // * - Redistributions of source code must retain the above copyright * // * notice, this list of conditions and the following disclaimer. * // * * // * - Neither the name of SEGGER Microcontroller GmbH * // * nor the names of its contributors may be used to endorse or * // * promote products derived from this software without specific * // * prior written permission. * // * * // * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * // * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * // * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * // * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * // * DISCLAIMED. * // * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * // * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * // * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * // * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * // * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * // * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * // * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * // * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * // * DAMAGE. * // * * // ********************************************************************** define memory with size = 4G; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block exidx { section .ARM.exidx.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; define block tls { block tbss, block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, readwrite access { }; do not initialize { section .non_init }; initialize by copy { section .fast }; place at start of FLASH { section .vectors }; place in SRAM { readwrite, zeroinit, block stack, block heap, block tls, section .non_init, section .fast }; place in FLASH { readexec, readonly, block exidx, block ctors, block dtors };