/* SPDX-License-Identifier: BSD-3-Clause */ /* * Copyright 2021 NXP * All rights reserved. * */ #include "flexspi_flash.h" uint32_t customLUT[ CUSTOM_LUT_LENGTH ] = { /* Read */ #if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) [ 4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18 ), [ 4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04 ), #elif defined( Macronix_MX25UM51345G ) [ 4 * NOR_CMD_LUT_SEQ_IDX_READ + 0 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xEE, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x11 ), [ 4 * NOR_CMD_LUT_SEQ_IDX_READ + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x08 ), [ 4 * NOR_CMD_LUT_SEQ_IDX_READ + 2 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0 ), #elif defined( Macronix_MX25UM51345G_2nd ) [ 4 * NOR_CMD_LUT_SEQ_IDX_READ + 0 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xEE, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x11 ), [ 4 * NOR_CMD_LUT_SEQ_IDX_READ + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x29 ), [ 4 * NOR_CMD_LUT_SEQ_IDX_READ + 2 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0 ), #elif defined( Cypress_S26KSxxxS ) [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x06 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 2 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0 ), #endif /* if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) */ /* Erase Sector*/ #if defined( ISSI_AT25SFxxxA ) || defined( WINBOND_W25QxxxJV ) [ 4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18 ), #elif defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) [ 4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xD7, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18 ), #elif defined( Macronix_MX25UM51345G ) || defined( Macronix_MX25UM51345G_2nd ) [ 4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xDE ), [ 4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0 ), #elif defined( Cypress_S26KSxxxS ) [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), /* ADDR 0x555 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80 ), /* DATA 0x80 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), /* ADDR 0x555 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00 ), #endif /* if defined( ISSI_AT25SFxxxA ) || defined( WINBOND_W25QxxxJV ) */ /* Erase whole chip */ #if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) [ 4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0 ), #elif defined( Macronix_MX25UM51345G ) || defined( Macronix_MX25UM51345G_2nd ) [ 4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F ), #elif defined( Cypress_S26KSxxxS ) [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 2 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 3 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80 ), /* 1 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 4 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 5 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 6 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 7 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), /* 2 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 8 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 9 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 10 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 11 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55 ), /* 3 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 12 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 13 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 14 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 15 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10 ), #endif /* if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) */ /* Page Program - quad mode or Octal mode */ #if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) [ 4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18 ), [ 4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0 ), #elif defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) [ 4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18 ), [ 4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x01 /*0x04*/, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0 ), #elif defined( Macronix_MX25UM51345G ) || defined( Macronix_MX25UM51345G_2nd ) [ 4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x12, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xED ), [ 4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04 ), #elif defined( Cypress_S26KSxxxS ) [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), /* ADDR 0x555 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0 ), /* DATA 0xA0 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80 ), #endif /* if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) */ /* Read status register */ #if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) [ 4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04 ), #elif defined( Macronix_MX25UM51345G ) [ 4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xFA ), [ 4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04 ), #elif defined( Macronix_MX25UM51345G_2nd ) [ 4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xFA ), [ 4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x20 ), [ 4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI + 2 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0 ), #elif defined( Cypress_S26KSxxxS ) [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), /* ADDR 0x555 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70 ), /* DATA 0x70 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0 ), #endif /* if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) */ /* Write Enable */ #if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) || \ defined( Macronix_MX25UM51345G ) || defined( Macronix_MX25UM51345G_2nd ) [ 4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0 ), #elif defined( Cypress_S26KSxxxS ) [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), /* ADDR 0x555 */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA ), /* DATA 0xAA */ [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02 ), [ 4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55 ), #endif /* if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) || defined( Macronix_MX25UM51345G ) || defined( Macronix_MX25UM51345G_2nd ) */ /* Enter OPI mode */ #if defined( Macronix_MX25UM51345G ) || defined( Macronix_MX25UM51345G_2nd ) [ 4 * NOR_CMD_LUT_SEQ_IDX_ENTEROPI ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x72, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20 ), [ 4 * NOR_CMD_LUT_SEQ_IDX_ENTEROPI + 1 ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0 ), #endif /* Write Enable OPI */ #if defined( Macronix_MX25UM51345G ) || defined( Macronix_MX25UM51345G_2nd ) [ 4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI ] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xF9 ), #endif };